While architectural security, especially side-channel attacks, on modern (micro-)processors are not new topics, their impact to computing systems are not fully understood by the academia and the industry. However, the widely usage of cloud computing and the introduction of Spectre and Meltdown attacks become the game changers. Multi-tenant cloud platforms, even with the latest compartment techniques, are still vulnerable to architectural side-channel attacks.?In this talk, we will first present LAZARUS, a novel technique to harden KASLR against paging-based side-channel attacks, e.g., Meltdown. In particular, our scheme allows for fine-grained protection of the virtual memory mappings that implement the randomization. We will then introduce a new microarchitectural timing covert channel using the processor memory order buffer (MOB). Specifically, we show how an adversary can infer the state of a spy process on the Intel 64 and IA-32 architectures when predicting dependent loads through the store buffer, called 4K-aliasing.?